System Features |
1. |
2KW OTP program memory |
2. |
128 Bytes data RAM |
3. |
One hardware 16-bit timer |
4. |
One hardware 8-bit timers with 6/7/8-bit PWM generation |
5. |
One set triple 11bit SuLED(Super LED) PWM generators |
6. |
One hardware comparator |
7. |
13 IO pins with optional pull-high / pull-low resistor |
8. |
Every IO pin can be configured to enable wake-up function |
9. |
Two Channel(PA4 & PB7) has two current options |
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IoL = 40mA/20mA IoH = 28mA/10mA @VBAT=5V, VOL=0.5V |
10. |
Clock sources: IHRC & ILRC & EOSC |
11. |
For every wake-up enabled IO, two optional wake-up speed are supported: normal and fast |
12. |
LVR Range: 1.8V ~ 4.5V |
13. |
External interrupt pins: PA0 / PB5, PA4 / PB0 |
14. |
Bandgap circuit to provide 1.20V reference voltage |
15. |
One low-power clock (NILRC) wake-up stopsys regularly. |
16. |
VCC input range: 4.3V~6.5V |
17. |
Programmable Charge Current Up to 500mA |
18. |
No MOSFET, Sense Resistor or Blocking Diode Required |
19. |
Constant-Current/Constant-Voltage Operation with Thermal Regulation to Maximize Charge Rate Without Risk of Overheating |
20. |
Preset 4.2V Charge Voltage with ±1% Accuracy |
21. |
Automatic Recharge |
22. |
C/10 Charge Termination |
23. |
2.9V Trickle Charge Threshold |
24. |
Standby power dissipation 57uA (VCC) in charging mode |
25. |
Up to 11-channel 12-bit resolution R-type*ADC with one channel comes from internal bandgap voltage. |
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CPU Features |
1. |
One processing unit operating mode |
2. |
86 powerful instructions |
3. |
Most instructions are 1T execution cycle |
4. |
Programmable stack pointer to provide adjustable stack level |
5. |
Direct and indirect addressing modes for data access. Data memories are available for use as an index pointer of Indirect addressing mode |
6. |
IO space and memory space are independent |
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