| System Features |
| 1. |
1.25KW OTP program memory |
| 2. |
64 Bytes data RAM |
| 3. |
One hardware 16-bit timer |
| 4. |
One hardware 8-bit timers with 6/7/8-bit PWM generation |
| 5. |
One set triple 11bit PWM generators and timers |
| 6. |
One hardware comparator |
| 7. |
7 IO pins with optional pull-high / pull-low resistor |
| 8. |
Every IO pin can be configured to enable wake-up function |
| 9. |
Clock sources: IHRC & ILRC |
| 10. |
For every wake-up enabled IO, two optional wake-up speed are supported: normal and fast |
| 11. |
LVR Range 1.8V ~ 4.5V |
| 12. |
External interrupt pins: PA0, PA4 |
| 13. |
Bandgap circuit to provide 1.20V reference voltage |
| 14. |
One low-power clock (NILRC) wake-up stopsys regularly. |
| |
|
| CPU Features |
| 1. |
One processing unit operating mode |
| 2. |
86 powerful instructions |
| 3. |
Most instructions are 1T execution cycle |
| 4. |
Programmable stack pointer to provide adjustable stack level |
| 5. |
Direct and indirect addressing modes for data access. Data memories are available for use as an index pointer of Indirect addressing mode |
| 6. |
IO space and memory space are independent |
| |
|