| System Features |
| 1. |
4KW Flash |
| 2. |
512 bytes EEPROM |
| 3. |
256 bytes SRAM(128*16 configuration) |
| 4. |
One hardware 16-bit timer |
| 5. |
Two hardware 8-bit timer with PWM generator |
| 6. |
Three hardware 11-bit PWM generator(PWMG0, PWMG1 & PWMG2) |
| 7. |
One hardware comparator |
| 8. |
Band-gap circuit to provide 1.20V reference voltage |
| 9. |
Up to 14-channel 12-bit resolution ADC with one channel comes from internal band-gap reference voltage or 0.25*VDD |
| 10. |
ADC reference high voltage: external input, internal VDD, Band-gap 1.2V, 1.6V, 2.0V, 2.4V, 3.0V, 4.0V |
| 11. |
One 1T 8x8 hardware multiplier |
| 12. |
Max. 22 IO pins with optional pull-high and pull-low resistor |
| 13. |
Two different IO Driving capability group to meet different application requirements |
| |
(1) PB4, PB7 Drive/Sink Current = 30mA/35mA (Strong) and 13mA/17mA (Normal) |
| |
(2) Other Ios (except PA5) Drive/Sink Current = 11mA(13 or20) mA |
| 14. |
Every IO pin can be configured to enable wake-up function |
| 15. |
Built-in 1/2 VDD LCD bias voltage generator to provide maximum 4x17 dots LCD display |
| 16. |
Clock sources: IHRC, ILRC and EOSC(XTAL) |
| 17. |
For every wake-up enabled IO, two optional wake-up speed are supported: normal and fast |
| 18. |
Eight levels of LVR reset ~ 4.0V, 3.5V, 3.0V, 2.75V, 2.5V, 2.2V, 2.0V, 1.8V |
| 19. |
Two selectable external interrupt pins by code option |
| |
|
| CPU Features |
| 1. |
8bit high performance RISC CPU |
| 2. |
98 powerful instructions |
| 3. |
Most instructions are 1T execution cycle |
| 4. |
Programmable stack pointer to provide adjustable stack level |
| 5. |
Direct and indirect addressing modes for data access. Data memories are available for use as an index pointer of Indirect addressing mode |
| 6. |
IO space and memory space are independent |
| |
|