| System Features |
| 1. |
2.5KW OTP program memory |
| 2. |
160 Bytes data RAM |
| 3. |
Maximum 13 IO pins can be selected as TOUCH PAD individually |
| 4. |
One hardware 16-bit timer |
| 5. |
Two hardware 8-bit timer with PWM generation |
| 6. |
Three hardware 11-bit PWM generators (PWMG0, PWMG1 & PWMG2) |
| 7. |
One hardware comparator |
| 8. |
Provide 1T 8x8 hardware multiplier |
| 9. |
14 IO pins with optional pull-high/pull-low resistor |
| 10. |
Every IO pin can be configured to enable wake-up function |
| 11. |
PA6/PA7/PB7 support large sink current: 80mA |
| 12. |
Bandgap circuit to provide 1.2V Bandgap voltage |
| 13. |
Up to 12-channel 12-bit resolution ADC with one channel comes from internal Bandgap refer |
| 14. |
Provide ADC reference high voltage: external input, internal VDD, Bandgap(1.20V), 4V, 3V, |
| 15. |
Clock sources: internal high RC oscillator(IHRC) and internal low RC oscillator(ILRC) |
| 16. |
For every wake-up enabled IO, two optional wake-up speed are supported: normal and fast |
| 17. |
Sixteen Levels of LVR reset: 4.5V, 4.0V, 3.75V, 3.5V, 3.3V, 3.15V, 3.0V, 2.7V, 2.5V, 2.4V |
| 18. |
Four selectable external interrupt pin |
| 19. |
Internal LDO for touch noise immunity |
| 20. |
One low-power clock (NILRC) wake-up stopsys regularly |
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| CPU Features |
| 1. |
One processing unit operating mode |
| 2. |
88 powerful instructions |
| 3. |
Most instructions are 1T execution cycle |
| 4. |
Programmable stack pointer to provide adjustable stack level (Using 2 bytes SRAM for one stack level) |
| 5. |
Direct and indirect addressing modes for data access. Data memories are available for use as an index pointer of Indirect addressing mode |
| 6. |
All data memories are available for use as an index pointer |
| 7. |
Separated IO and memory space |
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