| System Features |
| 1. |
2KW MTP program memory (programming cycle at least 1,000 times) |
| 2. |
128 Bytes data RAM |
| 3. |
One hardware 16-bit timer |
| 4. |
Two hardware 8-bit timer with PWM generator |
| 5. |
Three hardware 11-bit PWM generator |
| 6. |
Provide one hardware comparator |
| 7. |
14 IO pins and optional pull-high resistor |
| 8. |
Three different IO driving capability groups to meet different application requirement |
| 9. |
Optional IO drive capability for each port：normal drive and low drive |
| 10. |
Every IO pin can be configured to enable wake-up function |
| 11. |
Built-in half VDD bias voltage generator to provide maximum 4x10 dots LCD display |
| 12. |
Clock sources: IHRC, ILRC & EOSC (XTAL mode, 32KHz Reserved) |
| 13. |
For every wake-up enabled IO, two optional wake-up speed are supported: normal and fast |
| 14. |
Eight levels of LVR: 4.0V, 3.5V, 3.0V, 2.75V, 2.5V, 2.2V, 2.0V, 1.8V |
| 15. |
Two external interrupt pins |
| |
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| CPU Features |
| 1. |
One processing unit operating mode |
| 2. |
82 powerful instructions |
| 3. |
Most instructions are 1T execution cycle |
| 4. |
Programmable stack pointer and adjustable stack level |
| 5. |
Direct and indirect addressing modes for data access. Data memories are available for use as an index pointer of Indirect addressing mode |
| 6. |
IO space and memory space are independent |